Carbon-coating effect on the performance of photolithographically-structured Si nanowires for lithium-ion microbattery anodes

Introduction

The development of the lithium-ion microbattery (micro-LIB) as an energy storage for powering portable and smart devices aims to achieve high-energy density with a small areal footprint^1,2. Silicon (Si) has been an important material not only for many microelectronic devices but also for micro-LIBs. Direct fabrication of a micro-LIB on a chip using a Si wafer as a substrate enables monolithic integration with other microelectronic devices³. Furthermore, Si has been widely studied in conventional lithium-ion batteries (LIBs) for its potential as a high-energy-density anode thanks to the relatively high specific capacity (3590 mAh g⁻¹ for Li_3.75Si) and low potential (<0.4 V vs. Li/Li⁺)^4,5,6. Therefore, the utilization of Si in a micro-LIB is not solely intended as a substrate but also as an active material⁷. However, the challenge of utilizing Si is its extreme volume expansion upon Li insertion, which results in mechanical disintegration affecting electrical behavior and compromises capacity upon cycling^8,9,10. In turn, these collateral issues would limit the applicability of Si-based anodes in micro-LIBs. Various techniques have been applied to suppress the mechanical degradation including limiting the charging capacity¹¹, reducing the geometry of Si anode to micro/nano size^12,13,14, and combining Si with other materials^15,16.

The application of Si nanostructures to improve LIB performance has been demonstrated. In particular, Si nanowires attracted wide attention as they have a better ability to withstand volume change while providing an excellent electrical pathway, especially when they are directly grown on a current collector^17,18,19. Some of the reported Si nanowire anodes for conventional LIBs were fabricated as a slurry, in which the Si nanowires were blended in a mixture of binder, conductive material, and other additives^20,21,22. In this case, the transport of electrons from and to the current collector depends mainly on the conductive material. In contrast, an anode with direct electrical contact from Si nanowires to the current collector can be realized by bottom-up methods such as chemical vapor deposition (CVD)^23,24 or solution-based growth^25,26. However, these methods generally produce non-vertical and irregular nanowires. On the other hand, some top–down methods are not only well-established in semiconductor processing technology but also enable the production of vertical and regular arrays of nanowires. For a micro-LIB fabrication, this leads the integration with the existing semiconductor manufacturing to become seamless^27,28,29,30. Several studies have demonstrated three-dimensional (3D) Si structures fabricated by the combination of lithography and dry etching as an anode for micro-LIBs, showing promising performance^7,11,31. Furthermore, high controllability of Si nanowire geometry can be achieved by combining photolithography with cryogenic dry etching, which enables the fabrication of Si nanowires with smooth sidewalls using a single process³².

Although reducing the size of Si into micro-/nanostructure may minimize mechanical damage upon cycling, it does not solve the challenge of low electronic conductivity in conventional LIB applications. Moreover, the very low critical size at which the mechanical disintegration can be prevented (e.g., 150 nm in diameter³³) increases the complexity of the fabrication process. Therefore, combining Si nanostructures with other materials is necessary to overcome the issues by improving the conductivity as well as the structural integrity of Si anodes. Among various material choices, carbon-based materials have been widely incorporated with Si in conventional LIBs due to their excellent electrical and mechanical properties^34,35. In general, carbon is utilized to improve the reaction kinetics at the interface for energy storage devices³⁶. In conventional LIBs, carbon black is typically used in a slurry mixture as a matrix for Si nanowires. Carbon nanotubes (CNTs) are mixed with Si nanoparticles to improve the electrical conductivity of Si anodes³⁷. Si@C core-shell nanowires were incorporated to improve electrical conductivity and suppress mechanical failure³⁸. Laser-patterned Si@C particles can accommodate volume change and improve the cycling capability of the LIB³⁹. In micro-LIB applications, however, the methods commonly used in slurry-based C/Si anodes are not practically suitable for technologies employed in wafer-based processes. Instead, deposition techniques such as evaporation or sputtering are preferred. Among different deposition methods, thermal evaporation is considered simple and low-cost to deposit a thin film of amorphous carbon (a-C) on various substrates (e.g., planar and complex 3D structures including vertical Si nanowires). The ability to perform carbon coating on 3D Si nanowire anodes on a wafer using thermal evaporation enables the possibility to improve the performance of a micro-LIB as demonstrated in conventional LIBs. Table 1 summarizes the common differences between carbon-coated Si nanowires for conventional LIBs and micro-LIBs.

Table 1 Differences of carbon-coated Si nanowire anodes fabrication routes between conventional and micro-LIBs

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Here, we developed carbon-coated Si nanowire anodes for micro-LIBs, where their performance was deeply investigated with respect to the effect of carbon coating. First, photolithography and cryogenic dry etching were used to fabricate highly ordered Si nanowire arrays and fine-tune their sidewall shapes. Sequentially, a carbon coating was applied to the Si nanowires using thermal evaporation, in which the resulting carbon-coated Si nanowires were characterized in terms of their material properties. The electrochemical assessment was performed not only on the carbon-coated Si anodes but also on their pristine Si counterparts to study and validate the effect of carbon coating on the performance of Si nanowire anodes. Finally, a post-mortem analysis was conducted to enable a further discussion on the morphological changes of the anodes and subsequently provide insights on the possible occurring physical phenomena.

Results and discussion

Photolithographically structured silicon nanowire arrays

In general, the fabrication of Si nanowire anodes comprises two processing steps. The first step is the determination of nanowire lateral geometry and configuration by photolithography, followed by a cryogenic process of inductively coupled plasma reactive ion etching (ICP-RIE) to realize the vertical 3D structure. Figure 1a shows the fabrication steps of the Si nanowires. A Si wafer was cleaned to remove any contaminants prior to the photoresist deposition. The photoresist application was carried out by spin coating and subsequent baking to remove the solvent. Then, a pattern of dot arrays was transferred from a shadow mask (defined by chromium dot arrays with a diameter of 1 µm and a pitch of 4 µm on borosilicate glass) to the photoresist using ultraviolet (UV) exposure. The UV light broke the cross-linking of the polymer in the photoresist, while the polymer in the areas under the shadow remained cross-linked. A developer solution was then used to selectively remove the exposed areas, leaving the unexposed photoresist pattern on the Si substrate. The photoresist pattern was used in a subsequent etching step as a shield to protect the underlying Si from being etched. After the etching, the photoresist masks were removed, leaving the vertically aligned Si nanowire array structures on the Si substrate.

**Fig. 1: Fabrication of vertically aligned silicon (Si) nanowire arrays by photolithography and cryogenic dry etching.**

The ICP-RIE process at cryogenic temperature was deployed to provide the versatility of controlling nanowire geometry by ensuring smooth sidewalls. The other popular dry etching method is the Bosch process⁴⁰, which can also be utilized to produce Si nanowires. However, a more complicated optimization process is required to suppress the scalloping-sidewall effects resulting from the alteration of passivation and etching steps. The advantage of smooth sidewalls in cryogenic dry etching comes from the low temperature (e.g., −95 °C) that enables both surface passivation and etching to run simultaneously. Cryogenic dry etching is carried out by a plasma generated from O₂ and SF₆ gasses injected into a vacuum chamber while pressure is controlled. The resulting species (i.e., radicals and ions) then diffused to a sheath above the sample, and the ions were accelerated by an electric field to bombard the Si surface. The oxygen and fluorine radicals react with the Si surface to form volatile SiO_xF_y molecules, which are deposited as a stable passivation layer at the cryogenic temperature. Simultaneously, SF_x ions are bombarding the Si surface perpendicularly, removing the passivation layer at the bottom, and enabling a continued etching of Si by fluorine radicals there. The automated process can take place by setting-up suitable process parameters (e.g., substrate temperature, O₂ and SF₆ gas flow, chamber pressure, ICP power, radio-frequency (RF) power, and process duration). Each of the parameters contributes to the rate of passivation and etching. Finding the balance between the two is a crucial factor that determines the final geometry and surface finish of Si nanowires^27,41. As shown in Fig. 1b, positively tapered sidewalls can be achieved by setting the process condition, so that passivation layer formation is more favorable than the etching whilst the opposite condition will result in negatively tapered sidewalls. A relatively straight sidewall with a near −90° angle is the most preferable condition since it enables the formation of nanowires with a high aspect ratio.

To produce the desired Si nanowire geometry, process parameters have been optimized³². It has been demonstrated that various morphologies of Si nanowires can be fabricated by fine-tuning the process parameters. Here, we used an etching recipe comprising temperature of −95 °C, pressure of 0.8 Pa, ICP power of 500 W, RF power of 6 W, SF₆ flow of 118 sccm, O₂ flow of 13 sccm, and etching duration of 6 min. The result is Si nanowires with a height of 12.3 µm, top diameter of 630 nm, and positively tapered sidewall of 92.2°. Therefore, the aspect ratio of the nanowire can be calculated as 19.5, which is considered high. The 4 µm pitch of the nanowire arrays is unchanged since it was already determined by the mask pattern. However, compared to the diameter of the photoresist mask (i.e., 1 µm), there was a deviation, where the resulting top diameter of Si nanowires was reduced to 630 nm. This 37% shrinkage can be attributed to the lateral etching of the mask and the undercut (i.e., lateral etching of Si below the mask). The resulting Si nanowire arrays used in battery cell assembly and characterization are shown in Fig. 1c. Although the verticality of the Si nanowires is not perfect (i.e., non-straight sidewalls were realized), the slope of the sidewalls can be beneficial for the later carbon deposition step since it is assumed that it can better accommodate the deposition of material on the sidewalls considering the placement of the sample in the utilized thermal evaporation setup (see Fig. 2a).

Carbon coating

Maximizing the benefit of high surface area in Si nanowire anodes can be achieved by a conformal deposition of carbon. Here, carbon was applied to Si nanowire anodes using thermal evaporation. This method is commonly used to deposit carbon for a conductive layer in SEM imaging. It offers simplicity, low vacuum, and cost efficiency compared to the other carbon deposition methods. Moreover, a thin film of carbon can be deposited with respect to the surface profile (i.e., the topological information can be maintained in SEM imaging), hence, the conformal deposition on a 3D Si structure can be expected. Illustrations of a thermal-evaporation setup and the carbon-coating process are depicted in Fig. 2a. A Si nanowire sample was fixed on a holder and put inside a cylinder glass chamber. A vacuum pump evacuated the air inside the chamber to reduce the impurities during the process, which could also be unintentionally deposited on the sample. A carbon rod that was attached to a spring electrode was positioned at the top of the chamber against the bottom sample holder. An electric current was then flown through the carbon, producing heat energy and evaporating the carbon, which was followed by the emission of carbon molecules in all directions. The carbon vapor that reached the sample condensed, forming a thin film. The thickness of carbon coating is determined by the distance between the sample and the carbon rod as well as the process duration. Based on a calibrated deposition rate (~0.2 nm min⁻¹), the deposition process time was set at 50 min. Hence, the nominal thickness of carbon film is estimated to be ~10 nm. The typical carbon material deposited through thermal evaporation is amorphous⁴².

High-resolution FE-SEM images of Si nanowires were taken before and after carbon coating as shown in Fig. 2b, c, respectively. Figure 2b shows the 12.3 µm-high pristine Si nanowires with positively tapered sidewalls. Holes that appear on the top of Si nanowires can be attributed to the imperfection of the mask pattern from photolithography. In this case, the middle part of the mask had a much lower thickness with respect to the edges due to the diffraction effect during exposure. This formed donut-like shapes that were translated to holes on top of the nanowires during the cryogenic dry etching step. Due to the aspect-ratio-dependent-etching effect, it is expected that the depth of the holes only reaches several micrometers deep instead of going down to the bottom of the Si nanowires. Nevertheless, these holes should not significantly affect the comparison of electrochemical test results between pristine Si nanowires and carbon-coated Si nanowires. Particles that are present on the Si nanowire surfaces are assumed to be contaminants, which may be easily attached from air during sample handling (e.g., by electrostatic force⁴³). Energy dispersive X-ray spectroscopy (EDS) elemental mapping of the pristine Si nanowires (Fig. 2d) shows both Si and C signals, indicating that the Si nanowire sample was initially pristine. The weak C signal may come from the contaminants since the prior cryogenic dry etching process does not involve any C-containing substances.

Figure 2c shows the image of Si nanowires after carbon coating. Although the carbon deposition was expected to produce uniform thickness, it is evident that some clusters have adhered unevenly around the Si nanowires. The absence of such large substances in the pristine Si nanowires (Fig. 2b) suggests that they were produced by the thermal evaporation process instead of the prior Si nanowire fabrication process. From the EDS mapping, these clusters can be identified as an accumulation of carbon deposited on the Si nanowires (see Fig. 2e). These carbon clusters are distributed over the Si nanowire arrays, especially at the top part (see Supplementary Fig. 1a). From the X-ray diffraction (XRD) patterns (Supplementary Fig. 1b), no noticeable differences were observed between Si nanowires before and after carbon deposition. A typical XRD pattern of a-C has broad peaks at ~23° and ~43°^44,45,46,47. The lack of indication of these peaks may be attributed to the low amount of deposited carbon, compared to the peak that originated from the underlying crystalline Si nanowires (i.e., at 69°). Moreover, stronger C signals in the EDS mapping of carbon-coated Si nanowires (i.e., compared to those from pristine Si nanowires, as shown in Fig. 2d) were detected in a periodic arrangement at the position of the Si nanowire arrays (Fig. 2e). They exhibit higher C content at those particular points, while only weaker C signals come from the bottom area between the nanowires. Therefore, presumably due to the high aspect ratio of the Si nanowires, there is a higher probability that the carbon tends to be deposited on the sidewalls, especially at the higher part of the Si nanowires, than on their bottom part during thermal evaporation. In spite of the non-uniformity of carbon coating, the increase of wt% of C from 1.4% to 8.7% indicates that C has been successfully deposited on the Si nanowires (see Supplementary Fig. 1c–f).

Electrochemical characteristics

Electrochemical tests were carried out to evaluate the characteristics of both pristine and carbon-coated Si nanowire anodes. The Si anodes with an area of 1 × 1 cm² were assembled into coin-cell batteries with Li metal as the counter electrodes. Prior to any further electrochemical test, the samples were pre-lithiated by discharging the cell from 1.0 to 0.01 V at a constant current density of 0.05 mA cm⁻² for 10 h to ensure the formation of a surface electro-active region.

Figure 3a, b shows the cyclic voltammetry (CV) profiles of both pristine and carbon-coated Si between 0 and 1.5 V using a scan rate of 0.1 mV s⁻¹ in the first three cycles. In general, both anodes show similar reduction and oxidation potentials. The reduction (negative) peaks that emerge at ~240 mV (peak 1) in both anodes correspond to the lithiation of amorphous Si (a-Si)⁴⁸. In this case, the crystalline Si (c-Si) has already been transformed to a-Si during the pre-lithiation step. Thus, only the typical a-Si reduction peak appears in the CV profile. For the pristine Si nanowires (Fig. 3a), there are shoulders at ~175 mV (peak 2) that appear at the 1st and 2nd cycles but then disappear at the 3rd cycle, forming one broad lithiation peak at ~210 mV. In contrast, the carbon-coated Si nanowires exhibit two consecutive peaks at ~240 and ~140 mV (peaks 1 and 2 in Fig. 3b, respectively), which remain until the 3rd cycle. Weak reduction peaks at ~400 mV in both anodes (insets in Fig. 3a, b) are indicative of the solid electrolyte interphase (SEI) formation⁴⁹. Two oxidation peaks at ~400 mV (peak 3) and ~530 mV (peak 4) in both anodes can be attributed to the delithiation processes of a-Li_xSi, i.e., the partial and complete removals of Li from Si, respectively⁵⁰. Also in both anodes, there is a noticeable shift of the oxidation peak from ~350 mV in the 1st cycle to 400 mV in the 2nd and 3rd cycles. Both anodes show increased electrochemical activity with the number of cycles, which can be attributed to the gradual activation of Si upon the initial charge/discharge cycles^48,49,51. The slower increase of (de-)lithiation currents of carbon-coated Si compared to the pristine Si indicates that the activation process of c-Si is somehow hindered by the presence of carbon, in which the carbon alters Li⁺ movement characteristics⁴⁷.

**Fig. 3: Effect of carbon coating to the electrochemical characteristic of Si nanowire arrays.**

Figure 3c, d shows voltage profiles for various numbers of discharge/charge cycles of pristine and carbon-coated Si nanowires, respectively. The pristine Si nanowire anode achieved an areal capacity of 0.21 mAh cm⁻² in the 2nd cycle by discharging the half cell at 0.05 mA cm⁻². The discharge areal capacity was slowly decreased in the following cycles, indicated by areal capacity values of 0.20 mAh cm⁻², 0.19 mAh cm⁻², and 0.18 mAh cm⁻² in the 10th, 50th, and 100th cycles, respectively (Fig. 3c). The lower areal capacity in subsequent cycles may be caused by a pulverization of Si and a SEI build-up, which progressively reduces the amount of accessible Si and cyclable Li, respectively. However, thanks to their 3D structure, the available space surrounding the Si nanowires allows the Si to expand and shrink without significant stress and structural disintegration thereby keeping the reduction in the areal capacity minimal (i.e., compared to the planar Si as demonstrated in previous studies^19,31). In addition, differential capacity (dQ/dV) vs. voltage plots extracted from charge/discharge curves of pristine Si nanowires are shown in Supplementary Fig. 2a. A negative shoulder at ~0.29 V and a peak at ~0.23 V correspond to the transformation of a-Si to metastable amorphous Li–Si (a-LiSi) phases with the compositions of Li-50 at.% Si (P-I) and Li-30 at.% Si (P-II), respectively, through solid-state amorphization reactions⁵². On the other hand, positive peaks around ~0.47 V can be interpreted as de-alloying reactions. Since the anodes were only lithiated to 0.1 V, a-LiSi with a composition of Li-24 at.% Si (P-III) was not formed, indicated by the absence of a lithiation peak at ~0.07 V. Consequently, delithiation peaks at ~0.28 V also are not present, showing the absence of a phase transformation from P-III to P-II⁵². The three phases of Li–Si alloys (i.e., P-I, P-II, and P-III) correspond to LiSi, Li₇Si₃, and Li₁₃Si₄, respectively, based on the Li–Si phase diagram^53,54.

On the other hand, the carbon-coated Si nanowire anode was able to achieve an areal capacity of 1.46 mAh cm⁻² in the 2nd cycle, almost seven times higher than the areal capacity of pristine Si at the same cycle (Fig. 3d). This higher areal capacity can be attributed to the presence of carbon, which also reacts with the Li ions and provides more active sites for Li storage. In the pristine Si nanowire anodes, lithiation occurs more significantly on the sidewalls of the vertical Si nanowires than the (100)-oriented Si base⁵⁰. Whereas in the carbon-coated Si nanowires, all of the a-C, which consists of the deposited carbon on the top, sidewalls, as well as the base of the Si nanowire arrays, can equally act as lithiation sites, thus providing additional Li storage spaces for the anode besides the Si nanowires themselves. However, the areal capacity was significantly decreased in the 10th, 50th, and 100th cycles to 0.86 mAh cm⁻², 0.49 mAh cm⁻², and 0.3 mAh cm⁻², respectively. Since the addition of carbon seems to have a dominant contribution to the increase of the areal capacity of the anodes, we assume that this capacity decrease mainly was related to the degradation of the ability of a-C to store Li due to its irreversible capacity characteristic⁵⁵. Nevertheless, it is worth noting that even the lowest areal capacity of carbon-coated Si nanowire anodes (0.3 mAh cm⁻², in the 100th cycle) is still higher than the highest areal capacity of pristine Si nanowire anodes (0.21 mAh cm⁻², in the 2nd cycle), showing that the addition of carbon to Si nanowires contributes to an increase of the anode’s areal capacity in general due to the contribution from both active materials (i.e., carbon and Si nanowires). The dQ/dV vs. voltage plots of carbon-coated Si nanowires show more spikey profiles for both the lithiation and delithiation peaks (see Supplementary Fig. 2b). It can be related to an instability of the lithiation processes due to the observed non-uniformity of the carbon coating.

Electrochemical impedance spectroscopy (EIS) was carried out for both pristine and carbon-coated Si nanowire anodes as shown in Fig. 3e, f. Figure 3e displays the frequency response of both anodes before cycling. At this point, the anodes were not yet activated and SEIs have not yet been formed. The typical semicircle was not present, showing that both anodes are almost non-conductive and the electrochemical impedances are dominated by the ion diffusion process in the electrolyte. After 100 cycles, the impedances are significantly lower and semicircle characteristics are present in the Nyquist plots (Fig. 3f), indicating the activity of lithiation at the anodes. Interestingly, the carbon-coated Si nanowire anodes exhibit a larger impedance compared to their pristine counterparts. This behavior may indicate that the presence of carbon decreases the ionic transport between the electrolyte and the Si anode, which can be attributed to, for example, the degradation of the electrolyte and the formation of excessive SEI.

The comparison of charge/discharge capacities and Coulombic efficiency (CE) between pristine and carbon-coated Si nanowire anodes up to the 100th cycle is depicted in Fig. 4. It was assumed that charging-discharging the cells above 100 cycles would not significantly alter the areal capacity of both anodes, since the differences between subsequent cycles (quantified by a percentage change, see Supplementary Note 3) tend to reach values around zero. Hence, the cells are considered to be in their capacity stabilization period at the 100th cycle and no further test has been carried out as changes were not to be expected. As previously discussed, the pristine Si nanowire anode has an initial areal capacity of only 0.20 mAh cm⁻². However, it can maintain the value with minimal degradation (to 0.18 mAh cm⁻²) up to the 100th cycle (Fig. 4a). On the other hand, the carbon-coated Si nanowire anode can reach an almost ten times higher initial areal capacity of 1.84 mAh cm⁻² but degrades quite rapidly in the following cycles down to 0.30 mAh cm⁻² (Fig. 4b). Therefore, the pristine and carbon-coated Si nanowire anodes have 90% and 16.3% capacity retention, respectively. Another study by Bernard et al. demonstrated a similar behavior where a carbon coating on Si nanoparticle anodes exhibits a higher specific capacity with respect to the pristine Si at the early cycles, but it decreases significantly at the following cycles⁵⁶. In this case, an improvement in capacity retention can be expected by increasing the thickness of the carbon coating.

**Fig. 4: Cycling capability of Si nanowire arrays.**

Additionally, a distinct plateau appears between the 9th and 16th cycles in the carbon-coated Si nanowire anodes, in which the areal capacity is held at ~0.87 mAh cm⁻² before gradually decreasing again. The reason behind this phenomenon is unclear. However, the inhomogeneity of carbon deposition can influence the change of areal capacity in different cycles.

In terms of the capability to store and return Li, pristine and carbon-coated Si nanowire anodes possess high initial CE values of 97.5% and 99.5%, respectively. A high initial CE is crucial for Si-based anodes to determine their practical applicability⁵⁷. Moreover, the pristine Si nanowire anode has a relatively stable CE at ~97.4%, while the CE of the carbon-coated Si nanowire anode slightly fluctuates around ~99.5%. It seems that the degradation of carbon, which was indicated by the significant decrease of the areal capacity, was also accompanied by the consumption of active Li. Therefore, the fluctuation of CE may be attributed to the instability of SEI formation at each cycle, caused by the non-uniformity of carbon coating.

Changing the charge/discharge rate may also influence the areal capacity. The charge density of 0.05 mA cm⁻² used to cycle both pristine and carbon-coated Si nanowire anodes in this study was determined based on previous studies^31,32. A rate capability test by Nugroho et al. on pristine Si nanowire showed that a capacity retention of 76.7% at a higher charge density of 0.2 mA cm⁻² and a high-capacity retention of 97.1% was achieved³¹. This shows the ability of pristine Si nanowire arrays to withstand a high current rate. This excellent rate performance is expected to improve further by the introduction of carbon coating since the rate performance is related to the ability of the Si anode to withstand the volume change, especially at higher current rate. A study by Qi et al. demonstrated that the capacity retention of Si@C nanoparticle anodes is higher than that of the pure Si nanoparticle anodes⁵⁸. The improvement was related to the SEI generation that suppresses the large volume change of Si. Hence, future studies should aim at optimizing carbon-coating thickness on Si nanowire anodes as well as validating the rate performance with the presence of a more uniform carbon coating.

Table 2 shows the comparison between different Si anodes for micro-LIBs in half-cell configurations (i.e., using Li metal as the counter electrode). The utilization of 3D Si structures shows some benefits in terms of areal capacity. They possess higher accessible volumes of the active materials without sacrificing the mechanical integrity of the anodes. Although its areal capacity is not the highest, carbon-coated Si nanowire anode offers a potential to outperform the other types of 3D Si anodes only if it can maintain the initial areal capacity for longer cycles without significant degradation.

Table 2 Performances of various Si anodes for micro-LIBs with half-cell configurations

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Post-mortem analysis

Si nanowire anodes were further investigated after 100 cycles by dismantling the coin cells in delithiated condition and examining the Si anodes under FE-SEM. Figure 5a, b shows the comparison between cycled pristine Si nanowires and carbon-coated Si nanowires.

**Fig. 5: Post-mortem characterization of Si nanowire anodes after electrochemical test.**

The pristine Si nanowire anode is almost completely covered by some compacted granular substances, causing the morphology of the vertical Si nanowire arrays to be challenging to observe (see Supplementary Fig. 4a). However, some cracks over the covering substances as well as some open areas at which the Si nanowires have been detached (e.g., due to the mechanical force applied during cell disassembly) can be found on the sample, which expose the remaining Si nanowire morphologies (Fig. 5a). It is revealed that Si nanowires have been deformed from their original shapes. The most obvious change is the indication of anisotropic swelling, which is also reported in another study⁵⁹. In this case, the expansion characteristic of <100>-oriented Si nanowires has been exhibited, i.e., the swelling occurs to the four (110) facets on the sidewalls of the Si nanowires. The resulting cross-sectional Si nanowire morphology is flower-shaped, as compared to the circular shapes of the non-lithiated Si nanowires (see Fig. 2b). Nevertheless, the Si nanowires are able to preserve their free-standing behavior without detaching from the base. Moreover, thanks to the void spaces between the nanowires that provide rooms for volume expansions, concentrated stresses can be reduced. Hence, the Si nanowires can maintain their morphologies without being pulverized. This shows that the 3D structures can withstand the volume changes during 100 cycles of lithiation and delithiation while maintaining their structural integrity and electronic pathways to the current collector.

Similarly, the carbon-coated Si nanowires also exhibit good structural integrity upon cycling as can be easily observed in Fig. 5b. Here, no substance fills the gaps between the Si nanowires up to the top, hence the individual Si nanowires can still be identified (even though there are indeed some parts on the sample (~40%) that are covered by the substance, see Supplementary Fig. 4b). From the morphological point of view, the carbon-coated Si nanowires exhibit less profound swelling to the four (110) facets on the sidewalls compared to the pristine Si nanowire counterparts. This phenomenon indicates that the carbon coating can act as a mechanical support to constrict radial expansion of the Si nanowires⁶⁰.

Additionally, EDS elemental mapping was carried out for both pristine and carbon-coated Si nanowire anodes, as depicted in Fig. 5c, d, respectively. In both cases, C, O, P and F signals were detected on the samples, aside from the main Si signals, which are assumed to indicate the presence of the SEI. The formation of the SEI includes the decomposition of the electrolyte (i.e., lithium hexafluorophosphate (LiPF₆) diluted in a mixture of organic solvents consisting ethylene carbonate (EC), dimethyl carbonate (DMC), and diethyl carbonate (DEC)) at the anode-electrolyte interface. The chemical composition and thickness of the SEI are out of the scope of this study, though, it is typically composed of organic (lithium oxide (Li₂O), lithium carbonate (Li₂CO₃) and lithium fluoride (LiF)) and inorganic (lithium alkoxide (ROLi) and dilithium ethylene dicarbonate (Li₂EDC)) layers⁶¹ with a thickness ranging from 1 to 150 nm^62,63.

Considering the expected low thickness of the SEI compared to the gaps between the Si nanowires (~3.3 µm), it may be assumed that the covering substances that fill the gaps between the nanowires in the pristine Si nanowire anode (Fig. 5a) are mainly composed by a-Si instead of SEI. The repeated volume expansion/contraction occurring during lithiation/delithiation cycles seems to transform the solid pristine c-Si nanowires into granular a-Si compounds. At the same time, thin SEIs are also formed on these a-Si granules. The mixture of a-Si granules and SEIs from each pillar then meet, resulting in a compacted granular morphology that fills the gap in between and covers the top part of the Si nanowire array (see Supplementary Fig. 4a). Such gap-filling-up conditions were also observed in another study⁵⁰. Further work is necessary to unveil the more detailed mechanism of this phenomenon as well as to clarify the composition of the resulting substance.

Interestingly, the compacted granular a-Si that fills the gap between the nanowires was not found in the carbon-coated Si nanowire anodes. Instead, each Si nanowire can be distinguished from each other. Some substances can be seen either at the bottom part of the nanowires, bunching some nanowires together (Fig. 5b), or in some parts of the sample, covering the top of Si nanowires (Supplementary Fig. 4b). However, the morphology of these substances is seemingly different from those found in the pristine Si nanowire anodes. Here, they have a more solid characteristic as compared to the granular shape in the latter case. It can be deduced from the EDS mapping that these substances are SEI, as shown by the strong C, O, P and F signals that were detected in the respective areas (see Fig. 5d).

Figure 5e, f shows the XRD spectra of pristine and carbon-coated Si nanowire anodes, respectively, highlighting the difference in crystalline structures between the anodes before and after 100 charge/discharge cycles. Both anodes exhibit the amorphization of c-Si during lithiation/delithiation, indicated by the emerging humps between 15° and 35° of the 2-theta angles⁵⁰. The presence of crystalline Si is indicated by the dominant peak at 69° (i.e., <400>-orientation of crystalline Si), which comes from the underlying, not affected c-Si substrate³¹. This also supports the argument that the c-Si at the bottom was not significantly involved in the lithiation/delithiation processes. There are peaks at 33.3°, 56.1°, and 61.6° that appear in the cycled pristine Si nanowire anodes (Fig. 5e) yet absent in the cycled carbon-coated Si nanowire anodes (Fig. 5f). First, these peaks can be attributed to the crystalline Si phase since they can also be found in the XRD spectrum of planar Si(100) wafers (see Supplementary Fig. 1b). Because of the amorphization of the Si nanowires, these characteristic crystalline Si peaks may originate from the bottom area of Si nanowire anodes. Second, the reason behind their absence in the cycled carbon-coated Si nanowire anodes was probably due to the presence of solid and bulky SEI covering the bottom part of the Si nanowires (see label III at Fig. 5b, d), which may hinder the X-ray penetration. Hence, the characteristic peaks of crystalline Si may be suppressed, except for the dominant <400>-orientation at 69°. Such a hindrance occurs less frequently at pristine Si nanowire samples because of the availability of certain open areas at which there are no Si nanowires or any other substances (see Fig. 5a).

Putting everything together, the presence of a-C has impacts in at least two aspects. First, a-C helps to minimize the effect of volume expansion of the Si nanowires during cycling. It makes the effect of anisotropic swelling to be less profound. This is also indicated by the smoother Si nanowires compared to the rough and granular sidewalls of pristine Si nanowires (see insets in Fig. 5a, b). Furthermore, because the volume expansion is constrained, the development of compacted granular a-Si, which fills the gap between Si nanowires up to their top parts, can be significantly suppressed. Second, the presence of a-C at the interface between the Si nanowire surface and the electrolyte may influence the electrochemistry of lithiation. In this case, the resulting SEI is different from that found in pristine Si nanowire anodes, especially in terms of morphology. The SEI formed in the carbon-coated Si nanowires has a more solid (i.e., less granulated) and bulky (see arrows labeled as II and III in Fig. 5b, d) characteristics compared to the granular and porous SEI in the pristine Si-nanowire counterparts. These morphology differences may indicate that the formation of SEI in the presence of a-C consumes more electrolyte, which can irreversibly degrade its ionic diffusivity. This characteristic may also be responsible for the significantly higher impedance of the carbon-coated Si nanowire anode after 100 cycles compared to its pristine counterpart (see Fig. 3f).

Conclusions

micro-LIB anodes comprising carbon-coated Si nanowire arrays with a high aspect ratio of 19.5 and positively tapered sidewalls have been fabricated by combining photolithography, cryogenic dry etching, and thermal evaporation. The impact of carbon coating on the electrochemical performance of vertical Si nanowire anodes has been the focus of this study. The measured CV curves demonstrated a suppression of the activation process of the carbon-coated Si nanowire anodes compared to the pristine counterparts, which is shown by a slower increase of electrochemical activity at the first three cycles. From the galvanostatic charge/discharge curves, the initial areal capacity of carbon-coated Si nanowires is significantly higher (1.84 mAh cm⁻²), which can be attributed to the presence of carbon as a co-contributor of lithiation sites along with the Si nanowires themselves. In spite of the gradual decrease to 0.3 mAh cm⁻² throughout the 100 cycles, the final areal capacity of carbon-coated Si nanowire anode is still ~50% higher than the relatively more stable areal capacity of pristine Si nanowire anode (0.2 mAh cm⁻²), showing the benefit of carbon coating to the areal capacity. EIS measurements revealed that the carbon-coated Si nanowires have a higher impedance after 100 cycles. It is assumed that the irreversible capacity of a-C and the continuous consumption of electrolyte to form a SEI are responsible for the degradation of the areal capacity and the high impedance of the carbon-coated Si nanowire anodes.

Furthermore, from the post-mortem analysis, it is indicated that the presence of a-C seems to suppress the volume expansion of the Si nanowires and prevent the formation of excessive a-Si granules that fill the gaps between the nanowires up to their top parts. Nevertheless, the EDS mapping shows that solid substances are composed of SEI atomic components (i.e., C, O, P and F), leading to the assumption that SEI formation in the carbon-coated Si nanowires consumes more electrolyte. In summary, the utilization of a-C as a coating material for Si nanowires has the benefit of maintaining the structural integrity and improving the first 100 cycles’ capacity of the Si nanowires. However, it still suffers from a significant degradation of areal capacity and a high impedance due to the irreversibility of the SEI formed on the carbon-coated Si nanowires during cycling. Future works should aim for the optimization of carbon coating, including the conformality, uniformity, and thickness.

Methods

Silicon nanowire array fabrication

Silicon nanowires were fabricated from highly doped 2″ n-type Si(100) wafers (arsenic-doped, ρ = <0.005 Ω cm) from Siegert Wafer GmbH, Aachen, Germany. The Si wafers were cleaned using a 1:1 mixture of hydrogen peroxide (H₂O₂, 30%) and sulfuric acid (H₂SO₄, 96%) at 90 °C for 5 min to remove contaminants. Prior to patterning, the Si wafers were immersed in a buffered hydrofluoric acid (HF) solution for 2 min to remove native oxides and improve the adhesion of the photoresist. The patterning process was carried out by firstly applying a photoresist (AZ 5214 E diluted in AZ EBR with the ratio of 1:1, Microchemicals GmbH, Germany) using spin coating at 3000 rpm for 35 s, followed by soft baking on a hot plate at 110 °C for 50 s. The transfer of pattern from a shadow mask was carried out using an MJB4 mask aligner (SÜSS MicroTec SE, Garching, Germany) by exposing the sample to UV light generated by a Hg lamp (210 W) for 13 s. The photoresist was then developed in AZ 726 MIF developer (Microchemicals GmbH, Germany) for 40 s to remove the exposed areas, leaving circular array patterns. To fabricate the nanowires, an ICP-RIE process was carried out at cryogenic temperature using a PlasmaPro 100 RIE etcher (Oxford Instruments, UK). The process was carried out automatically by setting-up the temperature at −95 °C, pressure at 0.8 Pa, O₂ flow at 13 sccm, SF₆ flow at 118 sccm, ICP power at 500 W, RF power at 6 W, and etch time at 6 min. A dummy wafer of 4″ Si wafer was used as a holder for the ICP-RIE, the wafer was thermally oxidized to form 600 nm of SiO₂ layer to prevent it from being etched along the process. Fomblin oil was applied between the backside of the sample and the dummy wafer to provide good thermal conductivity. The 2″ Si wafer was cleaved into 1 × 1 cm²-sized pieces for further battery processing.

Carbon deposition

Deposition of carbon was carried out using an EC-32010CC carbon coater (JEOL, USA). The sample was put into a vacuum chamber without tilting against a carbon source. A current flowing through the carbon rod evaporates the carbon and releases carbon molecules. The carbon molecules were emitted in all directions and deposited on the sample. The process time was set at 50 min with a deposition rate of ~0.2 nm min⁻¹. The nominal thickness of the deposited carbon was assumed to be ~10 nm.

Material characterization

Scanning electron microscopy (SEM) images of the fabricated Si nanowires were captured by a Leica Cambridge S360FE SEM machine at room temperature. To provide a 3D image, the sample was tilted at 45°. The Si nanowire height (h_actual) was approximated by a calculation using the trigonometry identity ({h}_{{actual}}={h}_{{measured}}times sqrt{2}). Further investigations using field emission scanning electron microscope (FE-SEM) JEOL JIB-4610F were carried out after carbon coating and post-mortem to provide high-resolution topography images. Compositional information was obtained by EDS elemental mapping of Si Kα1, C Kα1, O Kα1, F Kα1, P Kα1 and S Kα1 using the same instrument. XRD data were obtained using an XRD Rigaku with Cu Kα (1.54 Ǻ) excited by an acceleration voltage of 40 kV, current of 30 mA, in parallel-beam geometry configuration.

Battery assembly and electrochemical characterization

To conduct the electrochemical characterization, the Si anodes were assembled into a half-cell configuration using CR2032 coin cells. The stacking of the coin cell comprises the bottom coin cell, Si anode, separator immersed by electrolyte, Li metal foil, spacer, and coin cell cap. A polypropylene separator (Celgard 2400) was used to isolate the Si from the Li metal electrode. The cells were filled by 50 µL electrolyte consisting of 1 M solution of LiPF₆ diluted in a 1:1:1 mixture of ethylene carbonate (EC), dimethyl carbonate (DMC), and diethyl carbonate (DEC). The fabrication of the battery cell was carried out inside a glovebox to maintain a low level of H₂O and O₂ (O₂ < 1 ppm, H₂O < 1 ppm) and rested for 5 h prior to any electrochemical tests. Pre-lithiation steps were carried out prior to charge/discharge cycles by discharging the cells from 1.0 to 0.01 V at a constant current density of 0.05 mA cm⁻² for 10 h to ensure the formation of a surface electro-active region. CV and areal capacity vs. voltage characteristics of the samples were measured using an automatic battery cycler WBCS 3000 (WonATech, Seoul, South Korea). The CV measurements were performed at a potential range of 0 to 2.5 V and a scan rate of 0.1 mV s⁻¹ for three cycles. The CV profiles were plotted only between 0 and 1.5 V to highlight the most important peaks, considering that there is no noticeable current response above 1.5 V. Galvanostatic cycling was carried out after the CV measurements at a voltage range of 0.15–1.0 V with a rate of 0.1 C (equals to 0.05 mA cm⁻²) for 100 cycles. EIS profiles were obtained with an Autolab PGSTAT302N (Metrohm, Herisau, Switzerland) before cycling and after 100 cycles of the half cells in the frequency range of 50 kHz to 0.1 Hz with an amplitude of 5 mV at room temperature.