On-chip solar power source for self-powered smart microsensors in bulk CMOS process

Microsensors with self-powered capabilities have substantial potential in Internet of Everything applications, as they are small and can operate independently without reliance on electrical grid supply, harvesting energy from the ambient environment instead^1,2,3,4. By implementing solar cells using standard CMOS processes, the size of these sensors would be reduced, as it integrates solar cells, energy harvesting systems, and sensor systems on a single chip, as shown in Fig. 1. The application modules can perform functions such as temperature sensing, image sensing, and simple signal processing and data transmission. The on-chip solar cells and energy harvesting systems form an on-chip power source that provides a stable, adapted working voltage to the application modules under certain lighting conditions. Compatibility and ease of integration into CMOS technologies are additional key requirements for realizing low-cost, large-scale systems for the consumer market⁵. This self-powered microsensor on a single chip can be manufactured using only standard CMOS processes and simple packaging, without any special fabrication processes.

Conceptual diagram of on-chip solar cells and energy harvesting system forming an on-chip power source to power single-chip smart microsensors. The proportion of the on-chip power source is enlarged with respect to others for illustration purposes.

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The evolution of low-power consumption sensor technology has led to the creation of CMOS sensors that function effectively on mere nano-watts of power, as shown through representative works in Table 1^6,7,8,9,10. Solar light, a pervasive and high-density energy source, with an energy density reaching up to 0.16 μW/lux·cm², could provide sufficient energy for microsensors through small size on-chip solar cells. The application of on-chip integrated energy harvesting systems to collect solar energy in microsensors has been successfully implemented in various studies^11,12.

The proposed on-chip power source comprises an energy harvesting system and solar cells. The overall energy conversion efficiency is determined by the voltage conversion efficiency of the energy harvesting system and the photoelectric conversion efficiency of the on-chip solar cells. The former one is well investigated by researchers, but few studies have been done for the latter.

Therefore, enhancing the photoelectric conversion efficiency of on-chip solar cells is an effective method to improve the performance of on-chip solar energy harvesting power sources. However, optimizing the efficiency of on-chip solar cells involves a tradeoff between photon-generated charge collection and electrode shadowing^13,14. Although larger electrodes improve conductivity and reduce internal resistance, they also increase cell shadowing due to larger metal coverage, compromising photoelectric conversion capability. Conversely, poor electrode designs degrade conductivity, raising internal resistance and decreasing photoelectric efficiency. While there have been studies using backside electrodes¹⁵ or transparent electrodes¹⁶ to mitigate electrode shadowing, such special processes raise manufacturing costs and integration challenges. Due to the constraints of standard bulk CMOS processes, it is important to optimize the surface electrode design of on-chip solar cells in order to enhance their photoelectric conversion efficiency. Existing studies focus largely on repurposing electrodes as gratings¹⁷ or capacitors¹⁸, with little exploration of optimized layouts to balance the internal resistance and shadowing.

A common ring electrode layout for on-chip solar cells, depicted in Fig. 2, has been widely utilized^19,20,21,22. Researchers apply this topology with vague rationale and random dimensions and positions. For example, one variant has a large ring electrode along the N-well inner edge, as shown in Fig. 2a, the other has a smaller ring for the electrode in Fig. 2b. In the literature, there is no theoretical analysis to prove which one is better and what dimensions are the optimized design. S₀ determining an optimal electrode layout remains an important open question.

a Layout diagram of a large ring-shaped surface electrode. b Layout diagram of a small ring-shaped surface electrode. c Electric field distribution of the square silicon N+ in the P-sub. There are one large and one small square ring electrodes inside the N+. The large ring is grounded as the cathode, and the small ring is connected to 1 V as the anode. d The lateral resistance model of a N-type highly doped silicon.

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Existing researches indicate that using Maximum Power Point Tracking (MPPT) technology combined with off-chip energy storage is a common strategy for energy harvesting. Employing an off-chip miniaturized battery storage system to collect excess energy during strong illumination can provide energy supplementation during insufficient light conditions to maintain normal operation of the load^23,24. However, in pursuit of a fully on-chip power source system, we have not utilized off-chip storage components. Under standard Bulk CMOS processes, on-chip energy storage is challenging to implement, leading us to abandon the strategy of storing excess energy. Instead, a direct output strategy is adopted. Therefore, to enable the chip to function under lower light conditions or to handle more load under the same illumination conditions, improving the photoelectric conversion capability of the on-chip solar cells is one of the most effective methods.

As the on-chip solar cells and the energy harvesting system are integrated on the same substrate, the P-type regions in the on-chip solar cells, namely PW and P-sub, are utilized as the cathode and grounded; whereas the N-type regions, DNW and N+, function as the anode for electrical energy output. Due to the voltage in the N-type region being lower than that in the P-type region under illuminations, the anode outputs a negative voltage, implying that the designed energy harvesting system needs to be capable of handling negative voltages. Additionally, as we adopt a direct output strategy, it necessitates the conversion of light energy into directly usable electrical energy. Surveys of some low-power sensors based on CMOS processes indicate that their operating voltages range from 0.8 to 1.2 V; therefore, the proposed energy harvesting system should output a voltage within this range. In this work, the energy harvesting system is designed to output a voltage of 1 V. Furthermore, in practical applications, as both the illumination environment and the load are dynamically changing, it is also necessary to ensure the stability of the 1 V output voltage.

This work investigates various surface electrode layouts to improve on-chip solar cell photoelectric conversion efficiency, examining tradeoffs between internal resistance and shadowing. An optimized electrode layout technique is proposed to minimize the internal resistance while reducing the shadowing. By applying the proposed surface electrode and highly doped region as interconnection, a segmented triple-well on-chip solar cell design is optimized based on a standard bulk CMOS process. Additionally, this work proposes an energy harvesting system that can convert the low negative voltage output from the optimized on-chip solar cells into a stable 1 V voltage, maintaining stability amidst variations in load or illumination.

This paper built theoretical models of square ring electrodes and center electrodes for the on-chip solar cells first. Through theoretical analysis, simulation, and measurement, we have demonstrated that the conductive ability of the CE is almost comparable to that of the RE. Due to its low shading rate and minimal metal-induced recombination rate, the CE exhibits more advantages over the RE as a surface electrode for on-chip solar cells. Then a 0.01 mm² segmented triple-well on-chip solar cell is designed using the CE to optimize the surface electrodes. Moreover, the interconnections between the sub-cells employ heavily doped areas to replace certain metal surface electrodes. This approach ensured that the shading rate of the designed on-chip solar cell remained consistently low. The measurement results revealed that, by optimizing the surface electrodes of the segmented triple-well solar cell, its photovoltaic conversion efficiency reaches an impressive 25.79%. This represents a 17.49% increase compared to the conventional unsegmented triple-well solar cell. These surface electrode optimization techniques demonstrate an effective improvement in the photovoltaic conversion efficiency of on-chip solar cells. An on-chip power source is implemented with the optimized solar cells and the proposed energy harvesting system. Measurement results demonstrate that the proposed on-chip power source can deliver an output voltage of approximately 1 V, with a maximum power conversion efficiency of 10.20% from end to end. The voltage monitoring and management module ensures stable operation of the on-chip power source under varying light conditions. Within the light intensity range of 20 klux to 100 klux, both the output voltage and conversion efficiency remain relatively stable. The characteristics of the proposed on-chip power source make it well-suited for powering smart micro-sensors in Internet of Things applications.

Resistance in silicon substrate

The internal resistance of on-chip solar cells includes lateral resistance vertical resistance of doped silicon region, and electrode resistance. However, the doped region is thin and the metal electrode resistance is much smaller than the lateral resistance. Consequently, the latter two components can be ignored and the lateral resistance within the doped silicon primarily dictates the internal resistance. In order to analyze the lateral resistance, the electric field distribution of the N+ thin layer needs to be obtained. Hence, a highly doped N-type square silicon with one small anode and one large cathode square ring electrode is simulated. Figure 2c depicts the surface’s electric field distribution. It can be seen that the equipotential lines between electrodes are primarily circular and become more square-like close to the electrodes. In 3D, the circular and square equipotential lines form their respective circular and square equipotential surface.

Based on the above simulation results, equivalent circuit models of on-chip solar cell with electrodes could be constructed. Figure 2d illustrates a square N-type highly doped silicon with one large anode and one small cathode square ring electrodes. The distances between the two electrodes to the center are L_n and L₀ respectively. Resistance r between the two electrodes can be expressed by r = ρ · L/S, where ρ is the doped region resistivity, L is the resistor length, and S is the resistor cross-sectional area, which is equal to the equipotential surface. From the cathode to the anode, S increases as the equipotential surface increases. In the circular region, S_C is approximated to be 2πlh, while in the square region, S_S is approximated to be 8lh, where l is the distance from equipotential surface to the center and h is the thickness of the doped region. Considering the circular equipotential surfaces, r_c is equal to (1); r_s for square surfaces, is equal to (2).

Through calculation and simplification, (1) and (2) can be reduced to (3) and (4) respectively.

Due to the coexistence of circular and square equipotential surfaces in reality, the resistance r must satisfy (5).

Square Ring Electrodes

Figure 3a illustrates an on-chip solar cell with a square N + /P-sub structure, where the N+ region utilizes a conventional large square ring electrode layout. The square ring electrode RE lies near the N+ edge at a distance L_RE to the center. The P-sub contact electrode encircles the N+ periphery. For simplicity, it is assumed that the equipotential lines are circular.

a The on-chip solar cell with a large square ring electrode in the N+ region. b Equivalent circuit of the on-chip solar cell with large square ring electrode. c The on-chip solar cell with a small central electrode in the N+ region. d The equivalent circuit of the on-chip solar cell with a central electrode.

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When the on-chip solar cell is under illumination, photogenerated carriers appearing in the region between L₀ and L_n can overcome the lateral resistance to reach the electrode.

On the other hand, in the central small region within L₀, experience similar electric field strengths in all directions, causing near-zero net electric force. Moreover, the central region has the largest lateral resistance to the electrode. These impede the large ring electrode from collecting these central carriers. The small inner central region contributes negligible photogenerated current. It can be regarded as a wasted region. Therefore, our model reasonably omits this L₀ inner area.

Figure 3b presents the equivalent circuit model for the on-chip solar cell’s large square ring electrode, with current sources denoting photogenerated current from the regions along each N+ doped equipotential surface. The lateral resistance between adjacent equipotential surface is R_n-i. Importantly, equipotential lines farther from the center correspond to a larger surface area, producing more photocurrent. Hence, outer current sources are larger than the inner ones. The expression for the equivalent resistance is given by r_RE = U_RE/I_RE, where U_RE is the voltage at node L_RE. By applying the superposition principle to analyze Fig. 3b, we can derive the expression for U_RE as U_RE = I_n × R_n + I_n-1 × (R_n + R_n-1)+…+I₀ × (R_n + R_n-1+…+R₀). Meanwhile, the current at node L_RE, I_RE, can be expressed as I_RE = I₀+…+I_n-1+I_n. Substituting U_RE and I_RE into the expression for the equivalent resistance r_RE = U_RE/I_RE yields the form of (6).

Applying (3), we sequentially determine the lateral resistance from L_n, L_n-1,…, L₂, L₁ to the N+ electrode respectively. Substituting them into (6) yields the N+ region’s equivalent resistance r_RE as (7).

where L_i = L₀ + idl. As dl approaches 0, n approaches infinity. After simplification, the N+ region’s equivalent resistance r_RE approximates to be (8). When accounting for near-electrode square equipotential surfaces, r_RE is expressed as (9), where k represents the percentage of the circular equipotential surface.

Square center electrodes

The on-chip solar cell shown in Fig. 3c is similar to the structure in Fig. 3a, except that the large square ring electrode in the N+ region is replaced by a small central electrode. The central electrode is located within the region L₀ from the center point, which is the region wasted by the large ring electrode case. The equivalent circuit is illustrated in Fig. 3d. Following the analysis approach described earlier, considering only circular equipotential surfaces, the equivalent resistance r_CE of the on-chip solar cell with a central electrode in the N+ region can be approximated as (10). In the case when circular and square equipotential surfaces are considered simultaneously, r_CE can be expressed as (11).

Equation (11) can be expanded to be (12). Subtracting (9) from (12) yields the difference Δr between r_CE and r_RE, as shown in (13). It can be observed that there is a constant difference between the lateral resistances of r_CE and r_RE. When the on-chip solar cell has a large area, that is, L_n/3L₀ is much larger than 2 (which can be easily satisfied), the constant term Δr can be neglected, i.e., r_CE ≈ r_RE. This implies that for on-chip solar cells with large areas, the layout configuration of CE and RE will result in nearly equivalent conductivity, but obviously CE has much lower shading rate. Therefore, in comparison to the RE, the CE has more advantages in terms of photoelectric conversion efficiency improvement.

Reducing metal1 contacts can effectively decrease the metal-induced recombination rate, thereby improving the photoelectric conversion capability of the solar cell²⁵. For on-chip solar cells with very small areas, even if the effect caused by the constant term Δr cannot be neglected, the CE has more benefits in terms of reducing shading rate and reducing metal-induced recombination rate compared to the small advantage gained by the RE in improving conductivity. Therefore, the layout configuration of CE is still recommended.

Surface electrode simulations

The theoretical models are validated using both simulation and experimental results with fabricated devices. 3D simulations are first performed to validate the theoretical derivations by constructing three distinct surface electrodes, RE1, RE2, and CE, on an N+/P-sub cell as depicted in Fig. 4. These electrodes are made of aluminum. The simulations model the influence of different electrodes on the load curve of a solar cell under vertical solar illumination with the same intensity. They can be divided into two groups. As shown in Fig. 4a, the first group of simulations have RE1, RE2, and CE individually serving as the N+ connecting electrode, while floating the others. The second group of simulations, as shown in Fig. 4b, c, and d, have RE1, RE2, and CE individually serving as the N+ connecting electrode, while eliminating the others. Figure 4e shows the simulation results. The first group results show that the short circuit current of CE is 12.0% higher than that of RE1, reflecting that even under the same shading rate, the smaller metal-induced recombination rate can enable CE to have a better performance. The second group of simulation results suggest that under the dual advantages of smaller metal-induced recombination rate and smaller shading rate, the short circuit current of CE in Fig. 4d is 15.4% higher than that of RE1 in Fig. 4b. The trends in the simulation results are consistent with our analysis, and the key parameter values are summarized in Table 2. We have included the carrier recombination, temperature, bulk lifetime, and doping profile diagrams corresponding to the six cases from Fig. 4a–d in Supplementary Fig. 1 for reference and discussion.

a Ring Electrode 1 (RE1), Ring Electrode 2 (RE2), and Center Electrode (CE) individually act as the N+ connecting electrode, while keeping other electrodes floating. b Only RE1 acts as the N+ connecting electrode. c Only RE2 acts as the N+ connecting electrode. d Only CE acts as the N+ connecting electrode. e Simulated I-V characteristic curves for the solar cell with the six conditions of surface electrodes from Fig. 4a–d. f Measurement results of load curve of three types of surface electrodes and Micrographs of the on-chip solar cell with 0.1 mm² in this case.

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Testing of surface electrodes

To undertake experimental studies, a 0.1 mm² on-chip solar cell of N+/P-sub using a standard 0.18 μm CMOS process is designed and fabricated, whose micrograph is shown in Fig. 4f. Similar to Fig. 4a, its surface electrodes are divided into RE1, RE2, and CE. The rest square rings in the N+ region are just floating metals. The size of CE L_CE uses the minimum metal1 size with single contact via regulated by the layout design rules. The ratio of N+ size to L_CE is 124. The on-chip solar cell is optically tested under vertical illumination of a Xenon lamp with 100 klux. The I-V curves of RE1, RE2, and CE are shown in Fig. 4f. It can be seen that there is no difference between the I-V curves of RE1, RE2, and CE, which agrees with the analysis and simulation results. Without RE metal shadowing, the performance of CE would improve.

Utilizing CE as the surface electrode for on-chip solar cells not only ensures conductivity but also reduces the metal coverage area and shadowing. Compared to the large number of contacts of RE, CE has only a small number of metal1 contacts, thereby improving the photoelectric conversion capability of the solar cell. Therefore, CE has more number of contacts of RE, CE has only a small number of advantages over RE. In addition, the simulation and measurement results also show that the on-chip solar cells with different sizes of concentric ring surface electrodes have only subtle differences in their conductivity.

Surface electrode optimization

Figure 5a shows the structure of a conventional triple-well on-chip solar cell, which consists of three doped regions with different concentrations and depths (N+, PW, DNW). Deep n-Well (DNW) is located in the P-Substrate (P-sub). P-well (PW) is located in DNW, and diffusion (N+) is located in PW. The conventional triple-well on-chip solar cell, labeled as Device I, has a size of 0.01 mm² and is fabricated using a standard 0.18 μm CMOS process, with its micrograph shown in Fig. 5b.

a The horizontal and vertical cross-sectional views of a conventional triple-well on-chip solar cells. b The micrograph of the conventional triple-well on-chip solar cell. c The layout of the proposed deeply segmented triple-well on-chip solar cell with the center electrode (CE) and N+ as interconnection. d The micrograph of the proposed deeply segmented triple-well on-chip solar cell. e The cross-sectional views of the proposed deeply-segmented triple-well solar cell sub-cells. f The measurement results of the load curve and power curve for the two 0.01 mm² triple-well on-chip solar cells. Device I is conventional one and Device II is the proposed one.

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Typically, PW is connected to P-sub as the ground of the solar cell, and DNW is shorted with N+ as the output terminal of the solar cell²⁶. The photoelectric conversion efficiency can be improved by segmenting on-chip solar cells’ large-doped regions into numerous small-doped sub-cells, because this provides larger vertical PN junction depletion region^27,28,29. For segmented on-chip solar cells, each sub-cell necessitates surface electrodes for photocurrent extraction and hence, the segmentation design increases electrodes extensively.

Based on (14), it is known that there is an optimal solution for the segmentation method of solar cells¹¹, where l₀ represents the side length of the small doped area unit after segmentation, a/b is the ratio of the transverse light sensitivity coefficient to the longitudinal light sensitivity coefficient, d₀ represents the spacing of the small doped area unit after segmentation, and S₀ represents the shadow area of the surface electrode. Therefore, according to (14), under other unchanged conditions, the smaller the value of S₀, the smaller the calculated value of l₀, which means more small doped area units are generated, resulting in more vertical edge light-sensitive PN junctions, and thus enhancing the photoelectric conversion capability of the on-chip solar cells.

Clearly, the large shadowing of RE inhibits the on-chip solar cell from being fully divided, while the small shadowing CE enables deeper segmentation of the on-chip solar cell for stronger photoelectric conversion capability.

A deeply segmented triple-well on-chip solar cell using the CE with a reduced light-blocking rate is designed, as shown in Fig. 5c. However, during the design process, a problem is encountered. The deep segmentation of the triple-well on-chip solar cell results in numerous sub-cells. The electrodes of similar types of sub-cells need to be connected and led out through metal wires. Although the CE can reduce the metal coverage area, the high density of sub-cell interconnections would increase the light-blocking rate of the on-chip solar cell. This leads to a substantial metal coverage on the deeply segmented triple-well on-chip solar cell, thereby hindering the CE effective enhancement on its photovoltaic conversion capability.

To address this issue, we adopted highly doped regions as interconnections for the sub-cells, replacing some of the metal electrodes. Among various doping options, N+ (P+) doping exhibits the highest conductivity. In the proposed deeply segmented triple-well on-chip solar cell, the N+ doped region is divided into four sections. One section employs a CE as the contact electrode, while the remaining three sections do not utilize metal as contact electrodes due to their small size. Instead, they are connected to the N+ doped region with the CE using N+ doping as the interconnection. Although N+ cannot compete with metals in terms of conductivity, the interconnected length of N+ is equal to the minimum distance of two adjacent N+ in the design rule and hence small enough to affect the performance. This ensures that the contact electrodes and interconnections formed by the highly doped N+ (P+) regions introduce minimal resistance. In other words, in the deeply segmented triple-well on-chip solar cell, the numerous sub-cells give rise to a large number of contact electrodes and N+ interconnections. They are in parallel connection, leading to a total low resistance. As a result, the design of using highly doped regions as some metal interconnections ensures that the surface electrodes have a low light-blocking rate.

The proposed deeply segmented triple-well on-chip solar cell, with a size of 0.01 mm², is fabricated using a standard 0.18 μm CMOS process, with its micrograph shown in Fig. 5d and the cross-sectional structure of its sub-cells shown in Fig. 5e. The load curve and power curve of the on-chip solar cells were measured under vertical illumination with a 100 klux Xenon lamp, and the measurement results are shown in Fig. 5f. The proposed design with optimized surface electrodes (Device II) demonstrates good performance, particularly in terms of photoelectric conversion efficiency, achieving 25.79%.

It’s worth noting that the calculation of the photoelectric conversion efficiency is based on the footprint area of the on-chip solar cell. The conventional unsegmented on-chip solar cell has a maximum conversion efficiency of 21.95%. This means the proposed design shows a 17.49% improvement over the conventional design. The comparisons with other works in the literature are summarized in Table 3. Additionally, Device II, with a footprint area of 0.01 mm², achieves a maximum output power of 2.58 μW, as shown in Fig. 5f. This value is comparable to the maximum output power of a single PN junction with a footprint area of 0.1 mm², as shown in Fig. 4f.

It is important to note that photogenerated carriers can also be produced outside the printed area, allowing the effective light-sensitive area of the on-chip solar cells to exceed the printed area. While it is crucial to avoid this phenomenon—known as bulk carrier contamination (BCC) effects—to ensure proper circuit operation³⁰, it can nonetheless enable the on-chip solar cells to generate additional short-circuit current.

On-chip power source

To meet the 1 V working voltage requirement of the application circuit, an energy harvesting system is implemented on the same chip as the on-chip solar cells. As illustrated in Fig. 6, this system mainly consists of a startup module, a voltage conversion module, a monitoring and voltage stabilization module, and a voltage reference module. The startup module consists of a low-threshold ring oscillator and a conventional bootstrap charge pump. The voltage conversion module includes a high-efficiency Dickson charge pump (main charge pump) and a voltage-controlled oscillator (VCO).

Conceptual diagram of on-chip solar cells and energy harvesting system forming an on-chip power source to power single-chip smart microsensors. The proportion of the on-chip power source is enlarged with respect to others for illustration purposes.

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When illumination causes the anode port of the on-chip solar cell to generate a negative voltage with an absolute value larger than 0.22 V, the start-up module converts and bootstraps the negative voltage at the anode port to a near 1 V positive voltage, powering the VCO to make it start working. Driven by the clock signal output from the VCO, the bootstrap charge pump starts operating, the V_out begins to rise and starts to output the power to the load.

To avoid the wastage of power, the startup module ceases operation. At this point, the bootstrap charge pump stops powering the VCO module, and the main charge pump begins to power it instead. The voltage reference module uses a simple three-transistor structure to generate the reference voltage required by the system. The monitoring and voltage stabilization module employs the resistive voltage division topology for sampling and compares the sampled voltage with the reference voltage, which ensures the output voltage is maintained at 1 V.

When fluctuations occur in the load size or light source intensity, the monitoring and voltage stabilization module adjusts the feedback signal T_A’s voltage to regulate the oscillation frequency of the VCO, thereby ensuring that the energy extracted by the energy harvesting system from the on-chip solar cells is just enough to maintain the output voltage at 1 V and support the power consumption required by the current load.

Using a 0.18 μm Bulk CMOS process, the on-chip power source comprising the energy harvesting system and the on-chip solar cells was fabricated, with its microphotograph shown in Fig. 7a. Under illuminations from a solar simulator, the on-chip power source is tested and the measurement results demonstrated that the energy harvesting system effectively converts the low negative voltage from Device II to a 1 V voltage. Figure 7b presents the relationship between the output voltage and output power of the on-chip power source with the load size. The measurement results indicate that under 100 klux illumination by the solar simulator, the output voltage of the on-chip power source is maintained between 1.05 V and 0.91 V as the load current changed from 0 to 1.11 μA. In this case, the power source can provide a maximum of 1.01 μW of output power to the application module of microsensors.

a Microscopic Photograph and Structural Schematic of the on-chip power source. b The relationship between the output voltage and output power of the on-chip power source with the load size under 100 klux solar simulator illumination. c The relationship between the output voltage of the on-chip power source and conversion efficiency with the light intensity.

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The relationship between the output voltage of the on-chip power source and the light intensity is shown in Fig. 7c. The measurement results indicate that the output voltage of the power source range is from 1.06 V to 0.96 V under light intensities of 20 klux to 120 klux. It should be noted that increasing the footprint of the on-chip solar cells can make the on-chip power source work under lower illuminations. Figure 7c also demonstrates the conversion efficiency from the incident light power to the output power of the on-chip power source under different light intensities, with an average conversion efficiency of around 9.45%, where the highest conversion efficiency reaches 10.20% at 120 klux. It is worth noting that in this work, Device II is only 0.01mm² as the on-chip solar cell in the on-chip power source. The footprint of the on-chip solar cell can be increased for higher power consumption requirements of the application module.

We utilized theoretical analysis and simulations to optimize the design. The enhanced on-chip solar cells and the corresponding energy harvesting system, forming the on-chip power source, were fabricated at a wafer foundry. Both the optimized on-chip solar cells and the on-chip power source were subsequently tested under illumination from a solar simulator.

Solar cell simulations

To compare the effects of different surface metals on the performance of on-chip solar cells, we performed 3D simulations using the Silvaco TCAD software (as shown in Fig. 4a–d). Due to the confidentiality of the foundry’s process parameters, the simulation parameters were estimated based on publicly available data: the doping concentrations for the N+ and P substrates were 10¹⁹ cm⁻³ and 2 × 10¹⁵ cm⁻³ respectively, with the N+ doping depth set to 0.1 μm. The metal surface parameters included a metal layer thickness of 0.1 μm, with aluminum as the material.

The simulations used the solar spectrum with a light incidence angle of 90 degrees. Boundary conditions were set with the top anode and bottom cathode as ohmic contacts, and the edges of the region were assumed to be insulated. The simulations were carried out at a temperature of 300 K. The physical models included in the simulation were the doping-concentration-dependent mobility model (Conmob), the electric-field-dependent mobility model (Fldmob), and the Shockley-Read-Hall recombination model (Consrh).

The simulation results for carrier recombination, temperature distribution, carrier lifetime, and doping profile of the on-chip solar cells are shown in Fig. 1 of the supplementary document. The detailed Silvaco simulation code is provided in the Methods section of the supplementary document, titled “The 3D simulation code for the on-chip solar cells.”

Circuit design and fabrication

The on-chip solar cell and its energy harvesting system were designed using Virtuoso software and fabricated by a foundry using a 0.18 μm CMOS process.

Illumination environment

The light source used in this study is a PL-X500D solar simulator xenon lamp. The light source is equipped with an AM1.5 filter to generate a spectrum consistent with natural sunlight, with an adjustable light intensity range from 20 klux to 120 klux. The distance between the sample and the light source was maintained at 15 cm, with the test environment set at 26 °C and 52% humidity. A Delixi commercial lux meter with model DLY-1801C, was used for light intensity calibration.

Electrical measurements

The electrical measurements were performed using the Keysight Technologies B2910BL single-channel source measure unit. The test setup for the measurement results shown in Fig. 4f is as follows: An on-chip solar cell, shown in Fig. 4f, was used as the sample. The P-sub was connected to GND, and the three surface electrodes on the N+ terminal (RE1, RE2, and CE) were sequentially used as the output terminals of the sample. The Ground Terminal of the source measure unit was connected to GND, and the Source Terminal was connected to the output terminal of the sample. Under 100 klux illumination, a current scan was made to obtain the load and power curves of the sample. The scan range was from 0 to −7 µA, with a step size of −0.1 µA.

The test setup for the measurement results shown in Fig. 5f is as follows: One on-chip solar cell from Fig. 5b and another one from Fig. 5d were used as the samples. Their P-well and P-sub terminals were short together to serve as GND, and the N+ and DNW terminals were short together to serve as the output terminal. The Ground Terminal of the source measure unit was connected to GND, and the Source Terminal was connected to the output terminal of the sample. Under 100 klux illumination, a current scan was made to obtain the load and power curves. The scan range was from 0 to −7.5 µA, with a step size of −0.1 µA.

The test setup for the measurement results shown in Fig. 7b is as follows: The P-well and P-sub of the on-chip solar cell in Fig. 5d were short together to serve as GND. The N+ and DNW terminals were both connected to the input terminal of the energy harvesting system shown in Fig. 7a, serving as the sole energy source for the system. The Ground Terminal of the source measure unit was connected to GND, and the Source Terminal was connected to the system’s output terminal, V_out. Under 100 klux illumination, a current scan was made to assess the system’s response to different loads, including V_out voltage and the system’s output power. The scan range was from 0 to 1.3 µA, with a step size of 0.05 µA.

The test setup for the measurement results shown in Fig. 7c is as follows: The P-well and P-sub of the on-chip solar cell in Fig. 5d were connected together to serve as GND. The N+ and DNW terminals were both connected to the input terminal of the energy harvesting system shown in Fig. 7a, again serving as the system’s only energy source. The Ground Terminal of the source measure unit was connected to GND, and the Source Terminal was connected to the system’s output terminal, V_out. The illumination intensity was varied from 20 to 120 klux, with a step size of 10 klux. During the measurement, the load was adjusted to determine the maximum end-to-end conversion efficiency (from incident light to load power conversion efficiency) at each light intensity, as well as the corresponding V_out voltage for the maximum conversion efficiency at each intensity.