Tailoring threshold voltage of R2R printed SWCNT thin film transistors for realizing 4 bit ALU

Introduction

The rapid advancement in microprocessor technology has played a pivotal role in reshaping our technological landscape, ushering in the integration of artificial intelligence (AI) into our daily lives. This evolution has given rise to edge computing^1,2,3, a paradigm that processes and analyzes real-time data locally, resulting in reduced energy consumption, optimized bandwidth utilization, and enhanced security. To implement edge computing effectively, everyday objects must be equipped with disposable smart labels containing microprocessors, wireless communication modules, memory, analog-digital converters, and sensors^4,5. Meeting the tremendous demand for these smart labels requires the development of flexible microprocessors (FlexM) on a scale exceeding several billion units per day. Therefore, innovative fabrication processes of the FlexM have been pioneered from the fabrication of an 8-bit FlexM with pentacene-based p-type thin film transistors (TFTs) on flexible plastic foil in 2012⁶ to a 32-bit ARM FlexM on flexible polyimide (PI) substrate in 2021⁷. However, since they are all bound by traditional photolithographic and vacuum deposition processes, they still face environmental challenges in emitting hazardous byproducts⁸ for manufacturing several billion per day. This has led to a growing need for sustainable high-throughput additive fabrication (SHAF) to address the demands of several billions of FlexM per day without emitting hazardous byproducts^9,10.

Therefore, printing technologies such as inkjet, screen, gravure, flexography, and offset have been considered to fabricate flexible electronic devices such as the SHAF^11,12,13,14. However, integrated logic gate-based flexible devices were only reported based on gravure¹⁵ and screen printing¹⁶, because all printed TFTs have difficulty controlling the electrical uniformity from device to device, particularly the threshold voltage (V_th). Thus, minimizing electrical variations in a large number of printed TFTs has been a big challenge for the last two decades in printed electronics because the rheological properties of employed electronic inks are vulnerable to humidity, temperature, and shear stress which influence not only the printing quality but also the electrical properties of printed TFTs. Among the reported printing methods to integrate TFTs, the roll-to-roll (R2R) gravure printing method stands out by printing p– and n-type single-walled carbon nanotube-based TFTs (p,n-SWCNT-TFTs) in terms of showing a way of repeatability in integrating complementary circuits with high throughput, high printing speed, and compatibility with inks in a wide viscosity range. Thus, the R2R gravure has been considered a promising candidate for manufacturing billions of FlexM units daily^17,18. To realize the R2R printed FlexM in the near future, existing limitations of wide variation and large V_th (~8 V) of the R2R printed p,n-SWCNT-TFTs should be first overcome to integrate more than eight logic gates (~ 50 p,n-SWCNT-TFTs) to demonstrate a concept of the SHAF¹⁵ without any photolithographic and vacuum deposition processes. The wide variation of V_th is mostly caused by positioning inaccuracy of overlay printed patterns and uneven topologies in printed layers, while the large V_th is due to the intrinsic electronic nature in the coexistence of metallic and semiconducting SWCNTs in the R2R printed p,n-SWCNT-TFTs^19,20. Moreover, the lack of efficient n-doping ink to realize R2R printed n-type SWCNT-TFTs with electrical properties matching to the R2R printed p-type SWCNT-TFTs also hindered the integration of more than 100 of the R2R printed p,n-SWCNT-TFTs. Therefore, narrowing down the V_th variation and tailoring V_th of the R2R printed p,n-SWCNT-TFTs to lower values are crucial for proving the concept of the SHAF via integrating more than eight logic gates by the R2R gravure printing method¹⁶. Thus, precise overlay printing registration accuracy (OPRA) and the R2R printed doping process should be attained at the same time²¹ to minimize V_th variations and tailor V_th.

In this paper, an arithmetic and logic unit (ALU) based on p,n-SWCNT-TFTs was selected and fabricated through R2R gravure printing process since the ALU is the most critical component to realize the FlexM for executing instructions that involve mathematical calculation and logical decision-making. Thus, an ALU consisting of 16 inverters, 8 XNOR gates, and 8 multiplexers (MUX) should be first designed and printed, especially concerning the variation and values of the V_th in the R2R printed p,n-SWCNT-TFTs²². To start fabricating the ALU, the existing R2R gravure printed p,n-SWCNT-TFTs (version 1 in Supplementary Table 1), including electronic inks in our team¹⁵ should first be employed to print an ALU, as a reference to evaluate a maximum number of integrated logic gates consisting of p,n-SWCNT-TFTs. Next, based on the attained variation and values of V_th by utilizing the OPRA and the R2R doping process in the existing R2R gravure printing system (1-bit ALU in Supplementary Table 2), narrowing the variation of V_th and tailoring V_th to lower values were achieved by improving the OPRA and the R2R doping process. To improve the OPRA, the role of registration mark superposition (ReMS) error on the gravure roll was investigated to figure out the relationship with observed OPRA errors. The schematic image of Fig. 1a represents existing gravure rolls with large ReMS errors, while Fig. 1b shows a new scheme of selecting the first gravure roll with minimized ReMS error as a reference roll to control the OPRA for printing 7 different patterns. Based on selecting the first gravure roll with minimized ReMS errors, the R2R printed p,n-SWCNT-TFTs would show low variations in V_th (Fig. 1c, d). Furthermore, by formulating the effective p,n-doping inks for tailoring V_th to lower values (Fig. 1c, d), the R2R printed complementary logic circuit consisting of p,n-SWCNT-TFTs having bottom-gate and bottom-contact structure (Fig. 1e) would show clear logic levels at the output by the same operation voltage. To prove the schemes shown in Fig. 1a, 1-bit, and 4-bit ALU were first designed and printed with previously reported p,n-doping inks and printing parameters of the R2R gravure to print p,n-SWCNT-TFT (version 1 in Supplementary Table 1 and R2R gravure system in Supplementary Table 2), and then analyzed parameters of printed devices to evaluate 1-bit and 4-bit ALU. Based on the evaluation, the OPRA and R2R doping processes were improved based on the scheme shown in Fig. 1b to print p,n-SWCNT-TFTs again with improved electrical characteristics (version 2 in Supplementary Table 1). By developing two methods in selecting the first gravure roll with minimized ReMS as the reference for reducing V_th variation via improving the OPRA and formulating effective p,n-doping inks to lower V_th values, the 4-bit ALU (Fig. 1f, g) was successfully fabricated via the R2R gravure printing process and shows a way of integrating many complementary logic circuits such as a microprocessor with large-scale integration of the R2R gravure printed p,n-SWCNT-TFTs.

Tailoring threshold voltage of R2R printed SWCNT thin film transistors for realizing 4 bit ALU — **Fig. 1: Schematic strategy to print large-scale 4-bit arithmetic and logic unit (ALU) starting from printed 1-bit ALU using a fully roll-to-roll (R2R) gravure printing process.**

Results

Fully R2R gravure printed 1-bit ALU

Since ALU is the fundamental part of the FlexM, which is responsible for arithmetic and logical operations²³, we designed a 1-bit ALU using R2R printed SWCNT-TFTs version #1 in Supplementary Table 1 by integrating 46 p,n-SWCNT-TFTs (23 for p-type and 23 for n-type). By employing the R2R gravure printing system, as shown in Fig. 1a and Supplementary Table 2, the 1-bit ALU was printed with 7 printing units via a continuous in-line R2R gravure printing process, using conventional gravure rolls. The obtained fully R2R gravure printed 1-bit ALU roll is shown in Fig. 2a with marking individual logic gates, namely XOR, NAND, sum/difference, and multiplexer. The cross-sectional scanning electron microscope (SEM) image of R2R printed SWCNT-TFT (700 nm thickness of gate, 2.25 µm thickness of dielectric, 450 nm thickness of drain/source, and 1.25 µm thickness of doping layer) is shown in Supplementary Fig. 1, and the transfer characteristics for the p,n-SWCNT-TFTs are shown in Fig. 2b with 8% and 9% variations of V_th, respectively for p,n-SWCNT-TFTs. Comprehensively characterized 46 p,n-SWCNT-TFTs are summarized in Supplementary Fig. 2, where the alteration of the channel length by 25% in the p,n-SWCNT-TFTs had a negligible impact on the V_th value and its variation, while the inefficient n-doping led to a wide variation in the V_th and decreased the mobility in the converted R2R printed SWCNT-TFTs. However, since the number of p,n-SWCNT-TFTs integrated into the circuit is merely 46, the analog output (logical operation, full adder, and subtractor operation) of the 1-bit ALU based on the selection lines of opcode [0] and opcode [1] are successfully obtained and summarized in Fig. 2c, d, and e. From those outputs, a slightly delayed signal along with output voltage level fluctuations was observed due to the mismatch between the pull-up and pull-down p,n-SWCNT-TFTs in complementary inverter logic. To show the easy connection of the printed flexible electronics, two printed 1-bit ALUs were simply connected as a ripple carry adder to demonstrate a 2-bit adder and subtractor operation, as shown in the schematic in Fig. 2f ① and the actual sample measurement setup in Fig. 2f ②. Following the 2-bit ALU operation, as shown in a truth table in Supplementary Table 3, we obtained the correct analog output voltage levels as drawn in Fig. 2g, h for 2-bit adder and subtractor, respectively, except for a few weak voltage levels owing to high V_th and a mismatch between the p,n-SWCNT-TFTs. Here, the device yield was 50% when we measured the function of 1-bit ALU by selecting a sample of 1-bit ALU (out of 16 1-bit ALUs) at every 1 m along 10 m of printed 1-bit ALU on polyethylene terephthalate (PET) roll (Supplementary Fig. 3). Based on the attained device parameters of the R2R printed 1-bit ALU, the 4-bit ALU was designed and printed using the same R2R gravure printing system (Fig. 1a and R2R gravure system in Supplementary Table 2 for 1-bit ALU). However, the R2R printed 4-bit ALU didn’t exhibit its intended functions mainly due to less tolerance over the inconsistent output signals resulting from V_th variation and the large V_th of the 156 of p,n-SWCNT-TFTs. Thus, the OPRA and R2R doping processes were scrutinized to minimize the V_th variation and shift V_th to a lower value.

**Fig. 2: R2R printed 1-bit ALU images and characterization.**

Improving the OPRA

To control the OPRA for machine direction (MD) and transverse direction (TD), the R2R controlling system utilized three cameras (summarized in Supplementary Fig. 4)¹⁸ to attain the rated OPRA error for the customized R2R gravure printer of ±50 µm at the MD and ±25 µm at TD, respectively, at a printing speed of 5.4 m/min for printing the 7 layers. Since the OPRA system tracks the registration markers engraved on the gravure roll as a reference, the manufacturing error in the position of each mark in the gravure roll directly affects the OPRA. There are 8 registration markers on a gravure roll, placed equally at the gap of 51 mm at an interval of 45° to the center of the gravure roll with a circumference of 408 mm. The error in each position of the registration markers is measured using a custom-designed superposition error measurement system²⁴ (Supplementary Fig. 5a) where the image and coordinates of the first marker are taken as the reference, and then, the gravure roll is rotated every 45° for seven times to reach the remaining seven registration markers to compare the coordinates of the marker positions with the reference coordinates of the first marker. The largest errors along MD and TD between the reference marker and the 7 remaining markers are called ReMS in MD and TD, respectively. The ReMS error in MD and TD of the seven gravure rolls to print 1-bit ALU was first examined as summarized in Supplementary Fig. 5b, which shows a maximum ReMS error of 50 µm in MD, and 20 µm in TD, respectively. Since the ReMS error in the gravure roll is obviously related to the error in the OPRA, it will consequently cause the V_th variation. However, under current technological limits in manufacturing the gravure roll, the ReMS errors in all gravure rolls cannot be controlled and are guaranteed to be less than 20 μm. Thus, instead of developing a groundbreaking technology in manufacturing the gravure roll with ultra-high precision, we developed a way of overcoming the technological limits by selecting the minimized ReMS error in the 1^st printing gravure roll (gate layer) because the 1^st printed registration markers have been used as a reference marker to control the OPRA until the 7^th printing step to completely print the ALU. Thus, we explored the effect of ReMS error on the OPRA in printed patterns based on the printed 1^st gate layer using two different gravure rolls with 17 µm and 44 µm ReMS errors, respectively, as the case of acceptable and unacceptable ReMS error in MD (Fig. 3a). By printing 2^nd dielectric layers on the 1st printed gate layer, Fig. 3b shows a clear dependence between the ReMS error and the OPRA error in the MD. The higher ReMS error (~44 µm) generates a larger OPRA error in the MD, even over 100 µm of registration error, causing the failure in integrating p,n-SWCNT-TFT. Based on this study, we confirmed that the attained OPRA error cannot be smaller than the ReMS error of the gravure roll for printing the first layer. Thus, the ReMS error in the 1^st printing gravure roll will be a key factor for minimizing V_th variations of the R2R printed p,n-SWCNT-TFTs by improving the OPRA. Besides the ReMS error, other factors such as nip force, web tension, and printing speed can affect the OPRA, and maintaining these factors with an acceptable range of variation was successfully carried out by the OPRA control system (Supplementary Fig. 4) under the R2R gravure printing condition (Supplementary Table 2) to provide consistency in the registration accuracy in MD and TD¹⁵.

**Fig. 3: Registration mark superposition (ReMS) error and its effect on OPRA.**

To estimate the V_th variation depending on the error range of the OPRA, we purposely printed three different types of p-SWCNT-TFTs with well-positioned source-drain layers and miss-positioned source-drain layers in TD and MD, respectively (inset images in Fig. 3c). A wide variation of V_th from 5.33 ± 2.10 V (mismatched TD of ±10 µm) to 8.77 ± 3.10 V (mismatched MD of ±20 µm) were observed while well aligned one gave 4.88 ± 1.00 V (Fig. 3c). Especially, the OPRA error in MD contributed to wider variation of V_th than that of TD and caused a positive shift in V_th for p-SWCNT-TFT as well. To further elucidate the impact of the OPRA on the electrical properties of printed devices, we purposely misaligned the active layer (p-SWCNT) to the MD by shifting 100, 200, and 300 µm from the center point of the printed dielectric layer, respectively, along the channel width of 1,400 µm while keeping the same printing conditions. The V_th variation increased from 10.12 ± 1.17 V for the well-aligned condition to 10.22 ± 1.21 V, 10.41 ± 1.15 V, and 11.26 ± 3.77 V as the active layers were misaligned by 100, 200, and 300 µm in MD, respectively (Fig. 3d). These results show that the large OPRA error in MD caused large V_th variation. Therefore, achieving the minimized OPRA error in both TD and MD for providing a narrow variation in V_th of the R2R printed p,n-SWCNT-TFTs is a key factor in increasing the number of integrated logic gates.

Improving R2R printed doping layers

V_th of the R2R printed SWCNT-TFT is influenced by several factors such as SWCNT diameter and chirality, the dielectric constant of the dielectric material with thickness of dielectric layer, TFT channel length and width, substrate roughness, nature of dopants, and environmental factors including humidity and oxygen. However, in this work, since the V_th and the on-off current ratio of the R2R printed SWCNT-TFT can be tailored by carefully selecting and printing appropriate doping inks²⁵, a polymer-based R2R gravure printable encapsulation ink was formulated and tested to shift the V_th of p-SWCNT-TFTs towards small V_th^{26,27,28,29,30}. Regarding poly-2-vinylpyridine (P2VP)-based p-doping ink, the V_th decreases with increasing concentration of P2VP while increasing the on-off current ratio (Fig. 4a) because P2VP lowered the Fermi level of SWCNT to 10 meV from the band edge causing the V_th of p-SWCNT-TFTs to shift toward the small V_th³¹. The mechanism behind the V_th shifting due to P2VP encapsulation has been further elaborated with energy band diagrams in Supplementary Fig. 6. However, the effective mobility decreased along with the V_th, suggesting that the encapsulated dopant will trap or scatter carrier charge²⁸. Although the mobility decreased with the increasing dopant concentration, the on-off current ratio increased by 300% from the undoped condition, as depicted in Fig. 4b. The improved on-off current ratio after the p-doping would be originated by shielding metallic SWCNT in the network and exclusion of ambient water molecules that act to enhance the p-channel conduction³². Regarding printing n-SWCNT-TFTs, there are several reports for converting p-SWCNT-TFTs to n-SWCNT-TFTs by using formulated n-doping inks based on ethanolamine, polyethylene amine^30,33,34,35, or 4-(2,3-Dihydro-1,3-dimethyl-1H-benzimidazol-2-yl)-N,N-dimethylbenzenamine, abbreviated as n-DMBI^36,37,38 because those molecules can transfer electrons to SWCNTs and increase the electron density in the conduction band of SWCNTs, making them behave with n-type properties. While developing the n-doping ink, we observed two major issues during the n-doping process: negative V_th shifting of n-SWCNT-TFT and instability in ambient conditions. Thus, a hybrid n-doping ink, formulated by implementing molecular dopant n-DMBI and 4,4′-methylene dianiline-based epoxy curing agent ZY-F51, called amine-ZY at here, and diethylene glycol monoethyl ether acetate as solvent has been developed to convert the p-SWCNT-TFT to n-SWCNT-TFT, while resolving the issue of the large V_th as shown in Fig. 4c. The formulated n-doping ink not only shifted the V_th towards a smaller V_th but also improved the on-off current ratio (Fig. 4d) owing to raising the Fermi level of SWCNT by electron-donating from n-DMBI³⁹. The underlying mechanism for the conversion from p-type to n-type SWCNT-TFT and the V_th shifting by printing n-DMBI with amine-ZY hybrid doping ink has been further elaborated in Supplementary Fig. 7.

**Fig. 4: Tailored threshold voltage (V_th) of R2R printed *p,n*-SWCNT-TFTs.**

Fully R2R gravure printed 4-bit ALU

After tailoring V_th of p,n-SWCNT-TFTs (TFT version #2.0 in Supplementary Table 1) and implementing 1^st gravure roll with minimized ReMS error, a 4-bit ALU was redesigned and printed using the R2R gravure system depicted in Supplementary Table 2. By arranging the adder/subtractor part of the 1-bit ALU in a ripple carry adder form, the first-bit operation was fed to carry input for the second bit, and this process continued iteratively up to the fourth-bit operation (Supplementary Fig. 8, including schematic block diagram and TFT-level circuit schematic). The designed 4-bit ALU includes a transmission gate-based 2:1 multiplexer (MUX) for selection lines as well as for logic shifter. Additionally, the number of integrated p,n-SWCNT-TFT has been reduced from 276 to 156 by employing the transmission gate. Supplementary Fig. 9 depicts the simulation results of printed p,n-SWCNT-TFT version 2.0 in Supplementary Table 1 and simulation output results for the 4-bit ALU. The schematic design encompasses three variations that focus on optimizing the p,n-SWCNT-TFT performance by adjusting the gate width, channel length, and channel width. The p,n-SWCNT-TFT dimensions from the 1-bit ALU design were used as a reference, and subsequent geometric scaling was employed to realize medium-size and small-size designs, scaled to 75% and 50%, respectively. These designs serve as a valuable foundation for reducing the size of p,n-SWCNT-TFTs (Supplementary Fig. 10).

The designed 4-bit ALU with p,n-SWCNT-TFT version 2.0 in Supplementary Table 1 was printed on a flexible PET substrate again with 6 different electronic inks and well-designed gravure cells, summarized in Supplementary Table 2. The printed 4-bit ALU with five different geometrical structures are shown in Fig. 5a in which all the logical blocks are shown only in the design with large-sized p,n-SWCNT-TFT. Figure 5b represents the transfer curves (V_GS–I_DS) of the large-sized p,n-SWCNT-TFTs for the 4-bit ALU. As a result of tailoring the V_th, the average V_th for the p,n-SWCNT-TFTs was reduced to 1.33 V and 0.06 V, respectively (Fig. 5c). Other key parameter distributions of the large-sized p,n-SWCNT-TFTs including transconductance, mobility, and on-off current ratio are similar to those of medium and small-sized p,n-SWCNT-TFTs, summarized in Supplementary Figs. 11 and 12. Decreasing the channel length results in improved mobility and transconductance, however, due to the presence of metallic SWCNTs, this also leads to an increase in the V_th variation. Therefore, we selected 4-bit ALU with large-size p,n-SWCNT-TFTs in this study and characterized all their functions.

**Fig. 5: R2R printed 4-bit ALU images and characterization.**

To validate the efficacy of tailored V_th, we characterized 4T-XOR logic gates for both pre- and post-modification samples. From the voltage transfer curves (VTCs), we observed a significant improvement in the noise margin and gain for the XOR logic circuit after implementing tailored V_th, with an increase of 24% and 70%, respectively, as drawn in Supplementary Fig. 13. The increase in noise margin and gain can be attributed to the reduction of the V_th variation of p,n-SWCNT-TFTs along with the enhancement of the on-off current ratio after the optimization of p– and n-doping processes. Overall, the output [0] to output [3] of the 4-bit adder operation with one of the digital inputs fixed at “1101” from the 4-bit ALU are summarized in Fig. 5d, where we confirmed the all-correct output analog signals for the adder operation. To demonstrate the operation of R2R printed 4-bit ALUs, the measurement setup for the characterization of 4-bit ALUs (large-sized p,n-SWCNT-TFTs, in-line structure) is drawn in Fig. 5e, where a custom-made jig was used to connect the 4-bit ALU with the power supply and Arduino-PC interface. Supplementary Movie 1 shows the output voltage swing during the measurement. Two inputs (A and B) were applied in the 4-bit ALU under 20 V of driving voltage. The digital input, B, is fixed as “1101”, while another digital input of A is varied from “0000” to “1111” to confirm the operation mode. Similarly, the output analog voltage levels for subtractor operation, right shift operation, and left shift operation of the 4-bit ALU are summarized in Supplementary Fig. 14. To prove the highest integration density of our work through all printing methods, Fig. 5f compares the number of TFTs integrated into a logical circuit realized under the currently available printing process^{40,41,42,43,44,45,46,47,48,49,50,51,52} and shows our work’s superiority (a red dotted circle mark in Fig. 5f). In addition, since heat dissipation is a critical factor to consider in printed electronic devices on flexible substrates such as PET, we analyzed the Joule heating effect on the PET due to the current flowing through a single R2R printed SWCNT-TFT during its on-state biasing i.e., V_GS and V_DS both held at −20 V. The on-current of the SWCNT-TFT and gate leakage current during the biasing is almost constant at 1.25 µA and 0.8 nA, respectively, as shown in Supplementary Fig. 15a. Similarly, the measurement setup with a thermal imaging infrared camera for heat dissipation measurement for the single R2R printed SWCNT-TFT biasing test and 4T-XOR logic gate test are shown, respectively, in Supplementary Fig. 15b, c. The experimental result and our calculation show a negligible temperature increase during the biasing test. These results show the possibility of operating R2R printed 4-bit ALU without generating serious heat.

Discussion

By implementing the R2R gravure printing method, we successfully showcased the SHAF concept and exemplified its application in fabricating 1-bit to 4-bit ALU. Notably, we achieved a yield of 50% for the 1-bit ALU, and a 2-bit ALU was realized by simply connecting two 1-bit ALUs in a ripple carry-forward layout. This exemplifies the feasibility of constructing larger logic circuits by combining multiple modular units of logic circuits based on R2R printed p,n-SWCNT-TFTs. However, due to a large error in MD and large V_th of R2R gravure printed 1-bit ALU, the same R2R gravure printing system could not be employed for printing 4-bit ALU. Thus, for this exploration of integrating more logic gates, we first identified the ReMS error as a key parameter for improving the OPRA of a multi-layer R2R printing system. After confirming the importance of the ReMS at the 1^st gravure printing roll, the OPRA in the MD and TD became constant at the level of ±50 µm and ±25 µm, respectively, at a printing speed of 5.4 m/min for printing the 7 layers by improving the precision of the ReMS at the 1^st gravure printing roll, and consequently, it could increase the scale of device integration by attaining more homogenous p,n-SWCNT-TFTs. Furthermore, the R2R gravure was fully utilized to print doping layers by implementing the p– and n-doping ink. For this purpose, P2VP-based p-doping ink was formulated to encapsulate the p-SWCNT-TFT to reduce the V_th through the interfacial charge density modulation³¹. Similarly, we also formulated a hybrid n-doping ink by mixing an amine-ZY-based dopant with an n-DMBI-based molecular dopant to shift the Fermi level of SWCNTs to the conduction band edge so that the electrons could be injected into the channel with minimal or no Schottky contact while effectively blocking holes. Through the implementation of R2R printed p– and n-doping layers for tailoring V_th, the average V_th of the p-SWCNT-TFT was reduced from 15.7 V to 1.3 V, and that of the n-SWCNT-TFT from −11.3 V to 0.06 V. With these improvements, we achieved a yield of 30% for the 4-bit ALU when we measured the adder function of the 4-bit ALU with large-sized SWCNT-TFTs at every 1 m along the 10 m of printed 4-bit ALU, reaffirming the SHAF as a highly efficient and cost-effective fabrication technology for flexible and printed electronics without the photolithographic and vacuum deposition processes.

Since the n-SWCNT-TFTs, converted from the p-SWCNT-TFTs with the R2R printed n-doping layer, have a smaller V_th and better on-off current ratio than the parent p-SWCNT-TFTs, we still have room for improving the p-SWCNT-TFTs by finding a suitable p-dopant with a strong electron-withdrawing property so that the off-current could be lowered to further enhance the on-off current ratio of the p-SWCNT-TFT and ultimately the noise margin of the implemented logic circuit. Furthermore, since the effectiveness of the SHAF can be significantly enhanced through improvements in the precision and resolution of the R2R gravure printing unit via minimizing the fluctuation in nip force and web tension, along with OPRA improvement to the few micrometer range, the printed p,n-SWCNT-TFT with smaller dimensions could be realized. Thus, the R2R gravure printed p,n-SWCNT-TFTs could also be scaled down to realize smaller channel length and width, which will reduce the parasitic capacitance and increase the switching speed to operate at a high-frequency range. At the same time, using a high network density of printed SWCNTs with enriched semiconducting properties can further increase the on-off current ratio enhancing the noise margin and gain along with higher charge carrier mobility. Furthermore, by reducing the thickness of the dielectric layer or increasing the dielectric constant of the dielectric ink, the R2R printed SWCNT-TFTs with higher transconductance and mobility can be realized to reduce the operation voltage. With these notable enhancements, the realm of the commercial viability of FlexM is inevitable by integrating over thousands of p,n-SWCNT-TFTs via the R2R gravure printing system.

In summary, we have developed two methods to improve p,n-type of R2R doping inks to tailor the V_th of p,n-SWCNT-TFTs and utilize the first gravure roll with minimized ReMS error to print the reference markers to minimize the OPRA errors among 8 gravure rolls by which the V_th values and device to device V_th variation were efficiently reduced to demonstrate a fully R2R gravure printed 4-bit ALU with the integration of 156 p,n-SWCNT-TFTs. This practical and novel approach can be further expanded to fabricate processors as proof of concept of SHAF.

Methods

Circuit simulation and design to pattern on gravure rollers

Berkely short-channel IGFET model 3 (BSIM3) of p,n-SWCNT-TFTs was created to match the transfer and output characteristics using Cadence Virtuoso Software (CVS). Using the modified TFT models, 1-bit and 4-bit ALU circuit layouts were designed and simulated in the CVS as described in the main text. The designed different patterns to print 1-bit and 4-bit ALUs circuits were engraved on gravure rolls (as shown in Supplementary Table 1) by Hando Machinery Co., Ltd., Korea.

Ink formulation and rheology characteristics

Inks for all the layers except the p-doping and n-doping were prepared and formulated similarly to our previously reported works¹⁵. The p-doping ink was prepared simply by dissolving poly(2-vinylpyridine) (P2VP, Mw, 37,500, Sigma Aldrich, USA) in 1-octanol (>99%, Sigma Aldrich, USA) with the weight ratio of 2 (P2VP):5 (octanol). The n-doping ink formulation process for 1-bit ALU is similar to our previous study¹⁵. However, in the case of 4-bit ALU, first, poly (methylmethacrylate) (PMMA, Mw, ~15,000, Sigma Aldrich, USA) was dissolved in diethylene glycol monoethyl ether acetate (ECA, 99.5%, Daejung, Korea) in 1(PMMA):5(ECA) weight ratio. Then, 20 wt% 4,4’-methylene dianiline-based epoxy curing agent ZY-F51(Xuzhou China Research Science and Technology Co. Ltd, China) and 1.5 wt% of molecular dopant 4-(2,3-Dihydro-1,3-dimethyl-1H-benzimidazol-2-yl)-N,N-dimethylbenzenamine (n-DMBI, 97%, Sigma Aldrich, USA) were added to the binder solution to mechanically stirring the mixture for 30 minutes. The surface tension and shear rate-dependent viscosity of the inks were measured using the SV-10 vibro-viscometer (A&D Co., Japan) and Du Nuoy tensiometer (ITOH, Seisakusho, LTD, Japan), respectively, in ambient conditions.

R2R gravure process for 1-bit and 4-bit ALUs

An R2R gravure printer with two printing units (i-Pen Co, Ltd, Korea) was used for printing all layers of the ALUs. The printing conditions (Supplementary Table 2, with the printing methods for 1-bit and 4-bit ALUs) follow our previous works^{15,18,53,54,55}. The oven temperature for drying the inks for all layers was 150 °C except for the n-doping layer (set to 80 °C).

1-bit ALU was fabricated by printing p,n-SWCNT-TFTs on a flexible PET substrate with a width of 250 mm and a thickness of 100 μm (AH71D, SKC, Korea) through the R2R gravure printer. Since the engraved gravure cell affected the printed layer’s topology and the edge waviness, the engraved layer structures were optimized and confirmed by employing them to print. The detailed engraved gravure cell structure for printing 1-bit ALU circuits with matched ink properties, and R2R gravure printing conditions (the web speed, angle of the doctor blade, and drying temperature) are summarized in Supplementary Table 2. The printing sequence is followed by (1) gate, (2) dielectric, (3) active, (4) insulator, (5) drain/source, (6) connection, and (7) n-doping. The R2R in-line printing was continuous with a web tension of 50 ± 3 N and a printing speed of 5.4 m/min (90 mm/s) to integrate the p,n-SWCNT-TFTs.

Briefly, the gate and dielectric layers were printed with Ag nanoparticles ink and BaTiO₃-based dielectric ink, formulated similar to our previous report¹⁴ along with having good surface topology avoiding coffee ring effect⁵⁶. After passing the drying chamber (150 °C for 14 s), the active ink was printed on a printed dielectric layer. To prevent short-circuit issues due to leakage at crossing wire points, the insulating ink was printed on each connecting point at the same printing speed. Then, the drain/source layers were overlay printed using the same Ag nanoparticle ink on the active layer. Again, Ag nanoparticle-based ink was printed on an insulator layer to connect each connecting point. Lastly, the n-doping layer was printed to convert the p-SWCNT-TFTs to n-SWCNT-TFTs. For printing 4-bit ALU, one additional printing layer (p-doping layer) was added to improve device parameters so that the total printing steps became 8. At the 7 and 8 printing units, p-doping and n-doping inks were selectively printed on the channel of p-SWCNT-TFTs to reduce the V_th and convert the p-type to n-type properties.

Electrical parameter extraction and device test

The transfer and output characteristics of the R2R printed p,n-SWCNT-TFTs were measured using a Keithley 4200A-SCS semiconductor characterization system (Tektronix Inc., USA). The 1-bit ALU output was characterized by using a function generator (AFG 3022, Tektronix, USA), a power supply (AK3003D, UvPOWER, Korea), and an oscilloscope (DPO 4034, Tektronix, USA).